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为满足雷达回波模拟器对时钟同步与同步时间安全性的需求，在现场可编程门阵列（Field Programmable Gate Array, FPGA）上采用精确时间协议（Precision Time Protocol,PTP）与SM4加密算法，实现回波模拟器之间的系统时钟同步，精确时间协议采用PTPv2协议版本实现。在FPGA上设计PTP主时钟与从时钟模块，使回波模拟器在组网时可以通过实际需求由软件配置为PTP主时钟或从时钟；PTP主时钟控制引擎采用超时控制机制，防止PTP主时钟在时钟同步的交互过程中由于延迟请求报文异常，导致状态机卡死；时钟偏移的计算采用归一到纳秒的方式，提高时钟偏移的计算精度；采用SystemVerilog语言设计SM4加密算法的加密模块、解密模块，实现对时间戳信息的加密、解密，解决时间戳信息传输的安全性需求；采用“PTP over UDP over IPv4”方式在传输层对PTP协议报文进行封装，实现PTP报文通过以太网进行接收与发送。将时钟同步系统在AMD XC7K325TFFG676 FPGA芯片上进行设计实现，测试结果表明：该时钟同步系统性能稳定，且在直连情况下同步误差均小于500 ns，满足设计指标要求。
Abstract：To satisfy the requirements of clock synchronization and synchronization time security for radar echo simulators, a PTP(Precision Time Protocol)and the SM4 encryption algorithm were implemented on a FPGA(Field Programmable Gate Array)to achieve system clock synchronization between echo simulators. The PTPv2 protocol version was adopted for implementation of the PTP. The PTP master clock and slave clock modules were designed on the FPGA, enabling echo simulators to be configured as PTP master clocks or slave clocks according to the actual demands during networking. In the design of the PTP master clock control engine,overtime control was adopted to prevent the PTP master clock from receiving abnormal delay request messages during clock synchronization interaction, which resulted in the freezing of the state machine. Normalization to nanoseconds was used to improve the calculation accuracy of the clock offset. The encryption and decryption modules of the SM4 encryption algorithm were designed using the System Verilog language to encrypt and decrypt the timestamp information, and meet the security requirements of timestamp information transmission. The PTP protocol messages were encapsulated at the transport layer by using the “PTP over UDP over IPv4”method to enable the reception and transmission of PTP messages through Ethernet. Finally, a clock synchronization system was designed and implemented on the AMD XC7K325TFFG676 FPGA chip. The test results show that the clock synchronization system is stable in terms of performance, and the synchronization error was less than 500 ns in the direct connection, meet ing the design specifications.
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基本信息:
DOI：10.20189/j.cnki.CN/61-1527/E.202502012
中图分类号:TN957.51;TN918.4
引用信息:
[1]李森.基于PTPv2协议的回波模拟器加密时钟同步系统设计[J].火箭军工程大学学报,2025,39(02):113-123.DOI:10.20189/j.cnki.CN/61-1527/E.202502012.
基金信息: